PCI-SIG DevCon and Where Samtec Fits - Semiwiki

PCI-SIG DevCon and Where Samtec Fits – Semiwiki

Time Stamp: June 7, 2023 9:00 AM
Source Node: 2707927

PCI SIG DevCon and Where Samtec Fits

PCIe (peripheral component interconnect express) is an interface standard for connecting high-speed components contained in PCs, MACs and other types of processors. Think graphics, storage arrays, Wi-Fi and the like. This communication standard has become incredibly popular. The first version of the standard was released in 2004 by Intel. Like many parts of computing architectures, newer generations delivered ever faster and more efficient performance. Gen 7 of the standard is currently in development. There is a key conference coming up on June 13 for all things PCIe. Just like DesignCON and MemCON, Samtec will be a force at this event. Read on to learn about PCIe, the PCI-SIG DevCon and where Samtec fits.

PCIe – Where Samtec Fits

Any communication standard requires hardware and software to implement the communication protocol, electronics to drive the communication channel and an interface to the communication channel and the physical medium. These last two parts are critical to completing the channel, and this is where Samtec provides a variety of solutions to get the job done.

Both the electrical and mechanical parts of the specification must be adhered to if the interface is to be robust and reliable. Samtec offers both connector and cable solutions that meet PCI Express® electrical and mechanical specifications. The high-level summary includes:

  • High-speed edge card sockets that support one, four, eight and sixteen PCI Express links and mate with PCI Express cable assemblies
  • PCI Express-Over-FireFly™ copper and optical cable assemblies for low latency, power savings and guaranteed transmission
  • An optical adaptor card is available with PCIe x16 edge card connector

For increased design flexibility, additional solutions are available that meet PCI Express electrical specifications with potential cost savings, including mezzanine board-to-board solutions and signal/power routing flexibility.

PCI-SIG DevCon – Where Samtec Fits

First, the vital stats for this important event:

PCI-SIG Developers Conference 2023

June 13-14

Santa Clara Convention Center

​Santa Clara, CA

You can register for the conference here. If you are developing any kind of computing device, PCIe is very likely to be part of the architecture, so this is key show to attend. What makes it even more compelling is registration is free if your company is involved in the standard, and over 900 companies are. Samtec is a Platinum Sponsor for the event. Here are some of the ways they are supporting the technical sessions:

Samtec and its partners will be participating in two technical sessions. Resident PCI Express technology expert Steve Krooswyk will detail exceptions of excursion compliance in cables and connectors. 

Martin Stumpf Rohde & Schwarz will detail the challenge of PCIe 5.0/PCIe 6.0 compliance in interconnect. He will discuss the partnership between Samtec, Rohde & Schwarz and Allion Labs.

The details for these two presentations are as follows:

Cable and Connector Compliance with Integrated Return Loss

Steve Krooswyk – Tuesday, June 13 | 3:30 PM – 4:30 PM PT

Upcoming PCIe 5.0 and 6.0 Cable and 6.0 CEM specifications are considering Integrated Return Loss (IRL) for excursion compliance.  Excursions may occur as compliance further reduces noise requirements and suppliers optimize high volume manufacturing practices.  Excursions up to a limit have minimal system impact.  IRL is not new, it’s history and process are reviewed, followed by simulation and measurement examples.

Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0

Martin Stumpf – Wednesday, June 14 | 9:00 AM – 10:0 AM PT

With 32 GT/s in PCIe 5.0 and 64 GT/s in PCIe 6.0, channel characteristics like loss, reflections and crosstalk are increasingly critical for the overall system performance. We will discuss performance requirements and implementations of PCIe 5.0 / 6.0 connectors and cable assemblies and the corresponding test setups and measurement methods to characterize and verify these interconnects. New metrics of ICN and IRL are included, as well as the related measurements. 

As the PCIe specifications define the performance requirements without the test fixtures, optimized test fixture design and accurate test fixture modelling and de-embedding is key for good measurement results. We will preview modern de-embedding techniques with accurate impedance modelling of lead-ins and lead-outs.

To Learn More

Register for this event now, you won’t want to miss it. And check out Samtec’s PCI Express® Interconnect Solutions brochure to learn more about how to a bring PCIe implementation to life. And that’s the story of PCI-SIG DevCon and where Samtec fits.

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