Advantages and challenges for heterogeneous integration in advanced packaging.
Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this as straightforward as chip-to-chip integration.
[embedded content]
Ed Sperling
(all posts)
Ed Sperling is the editor in chief of Semiconductor Engineering.
- SEO Powered Content & PR Distribution. Get Amplified Today.
- Platoblockchain. Web3 Metaverse Intelligence. Knowledge Amplified. Access Here.
- Source: https://semiengineering.com/multi-die-integration/
- 3d
- 7
- a
- About
- advanced
- advantages
- All
- All Posts
- and
- around
- Brings
- challenges
- chief
- Chips
- Connectivity
- content
- Director
- ed
- editor
- embedded
- Engineering
- Ether (ETH)
- Finally
- Forward
- functionality
- going
- host
- HTTPS
- improved
- in
- integration
- IT
- Layout
- Mainstream
- make
- Michael
- more
- multiple
- needed
- New
- packaging
- performance
- plato
- Plato Data Intelligence
- PlatoData
- popularity
- Posts
- ROW
- semiconductor
- straightforward
- Talks
- The
- thermal
- thumbnail
- to
- tools
- youtube
- zephyrnet
More from Semi Engineering
Accelerating Monte Carlo Simulations For Faster Statistical Variation Analysis, Debugging, And Signoff Of Circuit Functionality
Source Node: 2840222
Time Stamp: Aug 23, 2023
Hyperscale HW Optimized Neural Architecture Search (Google)
Source Node: 2600411
Time Stamp: Apr 21, 2023
Low Density Of LPDDR4x DRAM — The Best Choice For Edge AI
Source Node: 2750971
Time Stamp: Jul 5, 2023
