Formal Verification’s Usefulness Widens
Formal verification is being deployed more often and in more places in chip designs as the number of possible interactions grows, and as those chips are used in more critical applications. In the past, much of formal verification was focused on whether a chip would function properly. But as designs become more complex and heterogeneous, and as use cases change, formal verification is being utilized in everything from assessing the impact of partitioning to tracing the source of silent data corruption. It is even being used to identify possible vectors