Edge HW-SW Co-Design Platform Integrating RISC-V And HW Accelerators

A new technical paper titled “EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators” was published by researchers at Columbia University.

“We introduce a hardware/software co-design approach that combines software applications designed with Eigen, a powerful open-source C++ library that abstracts linear-algebra workloads, and real-time execution on heterogeneous System-on-Chip (SoC) architectures. We use ESP, an open-source SoC design platform that allows us to integrate the CVA6 RISC-V processor and custom hardware accelerators,” states the paper.

Find the technical paper here. Published May 2023.

Kuan-Lin Chiu, Guy Eichler, Biruk Seyoum, and Luca Carloni. 2023. EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators. In Proceedings of Cyber-Physical Systems and Internet of Things Week 2023 (CPS-IoT Week ’23). Association for Computing Machinery, New York, NY, USA, 209–214. https://doi.org/10.1145/3576914.3587510

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• Source: https://semiengineering.com/edge-hw-sw-co-design-platform-integrating-risc-v-and-hw-accelerators/