SystemVerilog

High-level synthesis (HLS) is a powerful tool for designing digital circuits. It allows engineers to quickly create complex circuits from high-level descriptions, such as C or SystemC code. However, the resulting circuits can be difficult to verify, as the design process is not completely deterministic. To address this problem, researchers at ETH Zurich have developed a formal verification approach for HLS circuits. The formal verification approach developed at ETH Zurich uses a combination of automated theorem proving and model checking techniques. The theorem prover is used to prove the correctness